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HT48R01/HT48R02/HT48R03 10-Pin MSOP I/O Type 8-Bit OTP MCU
Technical Document
* Tools Information * FAQs * Application Note -
HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series HA0049E Read and Write Control of the HT1380
Features
* Operating voltage: * Watchdog Timer * Program memory ROM: Up to 409615 * Data memory RAM: Up to 1608 * Buzzer driving pair and PFD supported * Power-down and wake-up functions reduce power
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V fSYS=12MHz: 4.5V~5.5V
* 7 bidirectional I/O lines and 1 input * Interrupt input shared with I/O line * 4 oscillator configuration options -
consumption
* Up to 0.5ms instruction cycle with 8MHz system clock
External crystal OSC External RC OSC Internal RC+I/O (PA5, PA6) Internal RC+RTC OSC (32768Hz)
at VDD=5V
* All instructions executed within one or two machine
cycles
* 14-bit or 15-bit table read instruction * Up to 8-levels of subroutine nesting * Bit manipulation instruction * Low voltage reset function * 10-pin MSOP package
* Internal RC oscillator - 3 frequency selections: 4MHz/8MHz/12MHz - 4MHz with 10% variation (2.2V~5.5V, 25C) - 8MHz with 10% variation (3.3V~5.5V, 25C) - 12MHz with 10% variation (4.5V~5.5V, 25C)
General Description
The HT48R01/HT48R02/HT48R03 are 8-bit high performance, RISC architecture microcontroller devices specifically designed for I/O control. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, Power-down and wake-up functions, Watchdog Timer, buzzer driver, as well as low cost, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem controllers, etc.
Selection Table
Part No. HT48R01 HT48R02 HT48R03 VDD 2.2V~5.5V 2.2V~5.5V 2.2V~5.5V Program Memory 1K14 2K14 4K15 Data Memory 648 968 1608 I/O 7 I/O, 1 Input 7 I/O, 1 Input 7 I/O, 1 Input Timer 8-bit1 8-bit2 8-bit2 External Interrupt 1 1 1 Buzzer O O O Stack 4 6 8 Package Types 10MSOP 10MSOP 10MSOP
Rev. 1.00
1
December 20, 2006
HT48R01/HT48R02/HT48R03
Block Diagram
P A 3 /IN T TM R1C In te rru p t C ir c u it STACK P ro g ra m ROM P ro g ra m C o u n te r IN T C M U X P r e s c a le r P A 2 /T M R 0 M U X fS
YS
M U
M U X P A 4 /T M R 1
fS X
YS
/4
TM R1 BZ1
TM R0C In s tr u c tio n R e g is te r TM R0 MP M U X D a ta M e m o ry BZ0 W DT p r e s c a le r In s tr u c tio n D ecoder ALU T im in g G e n e ra to r S h ifte r MUX PA1,PA3
M U
fS X
YS
/4 RTC OSC
W DT OSC
STATUS PAC PA P o rt A
OSC2 PA5
OS PA RE VD VS 6
C1 S S D In te rn a l RC OSC
ACC
LVR
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
/B /B /T /IN /T /O /O /R
Z MR T MR SC SC ES 1
Z
0 2 1
Pin Assignment
P A 3 /IN T 1 2 3 4 5 P A 2 /T M R 0 P A 1 /B Z P A 0 /B Z VSS 10 9 8 7 6 H T48R 01 1 0 M S O P -A PA4 P A 5 /O S C 2 P A 6 /O S C 1 P A 7 /R E S VDD P A 3 /IN T 1 2 3 4 5 P A 2 /T M R 0 P A 1 /B Z P A 0 /B Z VSS 10 9 8 7 6 P A 4 /T M R 1 P A 5 /O S C 2 P A 6 /O S C 1 P A 7 /R E S VDD
H T 4 8 R 0 2 /H T 4 8 R 0 3 1 0 M S O P -A
Rev. 1.00
2
December 20, 2006
HT48R01/HT48R02/HT48R03
Pin Description
Pin Name I/O Configuration Options Description Bidirectional 2-line I/O. Each pin can be setup as a wake-up input using a software register. Software instructions determine if each pin is a CMOS output or a Schmitt trigger input. Pull-high resistors can be connected using a pull-high software register. PA0/PA1 are pin-shared with the BZ and BZ buzzer function pins. Bidirectional single line I/O. PA2 can be setup as a wake-up input using a software register. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A pull-high resistor can be connected using a pull-high software register. This line is pin-shared with the Timer/event 0 counter input. Bidirectional single line I/O. PA3 can be setup as a wake-up input using a software register. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A pull-high resistor can be connected using a pull-high software register. This line is pin-shared with INT. Bidirectional single line I/O. PA4 can be setup as a wake-up input using a software register. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. A pull-high resistor can be connected using a pull-high software register. This line is pin-shared with the Timer/event counter 1 input.
PA0/BZ PA1/BZ
I/O
3/4
PA2/TMR0
I/O
3/4
PA3/INT
I/O
3/4
PA4/TMR1
I/O
3/4
OSC1/PA6 OSC2/PA5
I/O
Bidirectional 2-line I/O and oscillator pins. If configured as I/Os, software instructions determine if each pin is a CMOS output or a Schmitt trigger input. Pull-high resistors can be connected using a pull-high software register. A configuration option determines the choice of oscillator mode and I/O function. The four oscillator modes are: RC, Crystal, 1. Internal RC OSC: both pins configured as I/Os RTC or I/O 2. External crystal OSC: both pins configured as OSC1/OSC2 3. Internal RC + RTC OSC: both pins configured as OSC2, OSC1. 4. External RC OSC+PA5: PA6 configured as OSC1 pin, PA5 configured as I/O Note: When the system clock is sourced from the internal RC OSC, there are 3 frequency options (R) 12MHz, 8MHz and 4MHz.
PA7/RES VDD VSS
I 3/4 3/4
PA7 or RES Active low schmitt trigger reset input or PA7 input. 3/4 3/4 Positive power supply Negative power supply, ground
* All pull-high resistors are controlled by an register option bit.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C IOH Total............................................................-100mA
Rev. 1.00
3
December 20, 2006
HT48R01/HT48R02/HT48R03
D.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 VDD Operating Voltage 3/4 3/4 IDD1 Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (Crystal OSC, RC OSC) Operating Current (Internal RC+RTC OSC, Normal Mode) Operating Current (Internal RC+RTC OSC, Normal Mode) Operating Current (Internal RC+RTC OSC, Normal Mode) Operating Current (Internal RC+RTC OSC, Slow Mode) Standby Current (WDT Enabled, RTC Off) Standby Current (WDT Disabled, RTC Off) Standby Current (WDT Disabled, RTC On) Input Low Voltage for PA0~PA6, TMR0, TMR1 and INT Input High Voltage forPA0~PA6, TMR0, TMR1 and INT Input Low Voltage (PA7/RES) Input High Voltage (PA7/RES) Low Voltage Reset 1 Low Voltage Reset 2 Low Voltage Reset 3 I/O Port Sink Current 5V IOH 3V I/O Port Source Current 5V RPH 3V Pull-high Resistance 5V 3/4 VOH=0.9VDD 3V 5V 3V 5V 5V 3V 5V 3V 5V 5V 3V 5V 3V No load, system HALT 5V 3V No load, system HALT 5V 3V No load, system HALT 5V 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3V 3/4 3/4 3/4 3/4 Configuration option: 4.2V Configuration option: 3.15V Configuration option: 2.1V VOL=0.1VDD No load, fSYS=12MHz No load, fSYS=8MHz No load, fSYS=12MHz No load, fSYS=8MHz Conditions fSYS=4MHz fSYS=8MHz fSYS=12MHz No load, fSYS=4MHz Min. 2.2 3.3 4.5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 3.98 2.98 1.98 4 10 -2 -5 20 10 Typ. 3/4 3/4 3/4 1 2.5 2 4 6 1 2.5 2 4 6 10 20 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 4.2 3.15 2.1 8 20 -4 -10 60 30 Max. 5.5 5.5 5.5 2 5 4 8 12 2 5 4 8 12 20 40 5 10 1 2 5 10 0.3VDD VDD 0.4VDD VDD 4.42 3.32 2.22 3/4 3/4 3/4 3/4 100 50 Ta=25C Unit V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V V V V V V mA mA mA mA kW kW
IDD2
IDD3
IDD4
No load, fSYS=4MHz
IDD5
IDD6
IDD7
No load, fSYS=32768Hz
ISTB1
ISTB2
ISTB3
VIL1 VIH1 VIL2 VIH2 VLVR1 VLVR2 VLVR3 IOL
Rev. 1.00
4
December 20, 2006
HT48R01/HT48R02/HT48R03
A.C. Characteristics
Symbol Parameter Test Conditions VDD 3/4 fSYS1 System Clock (Crystal OSC, RC OSC) 3/4 3/4 Conditions 2.2V~5.5V 3.3V~5.5V 4.5V~5.5V Min. 400 400 400 10800 7200 3600 3/4 0 0 0 45 32 1 3/4 1 0.25 3/4 0.035 Typ. 3/4 3/4 3/4 12000 8000 4000 32768 3/4 3/4 3/4 90 65 3/4 1024 3/4 1 3/4 3/4 Max. 4000 8000 12000 13200 8800 4400 3/4 4000 8000 12000 180 130 3/4 3/4 3/4 2 100 3/4 Ta=25C Unit kHz kHz kHz kHz kHz kHz Hz kHz kHz kHz ms ms ms tSYS ms ms mV V/ms
4.5V~ 12MHz, Ta=25C 5.5V fSYS2 System Clock (Internal RC OSC) (10%) 3.3V~ 8MHz, Ta=25C 5.5V 2.2V~ 4MHz, Ta=25C 5.5V fSYS3 System Clock (32768 Crystal) 3/4 3/4 fTIMER Timer I/P Frequency (TMR) 3/4 3/4 tWDTOSC tRES tSST tINT tLVR VPOR RPOR 3V Watchdog Oscillator Period 5V External Reset Low Pulse Width System Start-up Timer Period Interrupt Pulse Width Low Voltage Width to Reset VDD Start Voltage to Ensure Power-on Reset VDD Rise Rate to Ensure Power-on Reset 3/4 3/4 3/4 3/4 3/4 3/4 3/4 2.2V~5.5V 3.3V~5.5V 4.5V~5.5V 3/4 3/4 3/4 Wake-up from HALT 3/4 3/4 3/4 3/4
Note: tSYS=1/fSYS1, 1/fSYS2 or 1/fSYS3
Rev. 1.00
5
December 20, 2006
HT48R01/HT48R02/HT48R03
Functional Description
Execution Flow The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The program counter controls the sequence in which the instructions stored in program memory are executed and its contents specify the full range of program memory. After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m C lo c k T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a readable and writable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required.
O S C 2 ( R C o n ly ) PC PC PC+1 PC+2
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution Flow Program Counter *11 0 0 0 *10 0 0 0 *9 0 0 0 *8 0 0 0 *7 0 0 0 *6 0 0 0 *5 0 0 0 *4 0 0 0 *3 0 0 1 *2 0 1 0 *1 0 0 0 *0 0 0 0
Mode Initial Reset External Interrupt Timer/Event Counter Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter+2 *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
Program Counter Note: *11~*0: Program Counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: PCL bits
For HT48R01, the Program Counter is 10 bits wide, i.e. from *9~*0 For HT48R02, the Program Counter is 11 bits wide, i.e. from *10~*0 For HT48R03, the Program Counter is 12 bits wide, i.e. from *11~*0 Rev. 1.00 6 December 20, 2006
HT48R01/HT48R02/HT48R03
Program Memory - ROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 102414 bits for the HT48R01, 204814 bits for the HT48R02 or 409615 bits for the HT48R03, addressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage:
* Location 000H * Location 008H
This location is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
* Location 00CH (HT48R02/HT48R03 only)
This area is reserved for program initialization. After chip reset, the program always begins execution at location 000H.
* Location 004H
This location is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Table location
This area is reserved for the external interrupt service program. If the INT input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004H.
Any location in the program memory can be used as look-up tables. The instructions TABRDC [m] (the current page) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the other bits of the table
000H 004H 008H 00C H H T48R 03 D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
000H 004H 008H
H T48R 01 D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
000H 004H 008H 00C H P ro g ra m M e m o ry
H T48R 02 D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
n00H nFFH
L o o k - u p T a b le ( 2 5 6 w o r d s )
P ro g ra m M e m o ry P ro g ra m M e m o ry L o o k - u p T a b le ( 2 5 6 w o r d s )
n00H 300H 3FFH L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 4 b its N o te : n ra n g e s fro m 0 to 3 nFFH
L o o k - u p T a b le ( 2 5 6 w o r d s )
n00H nFFH
700H 7FFH
L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 4 b its N o te : n ra n g e s fro m 0 to 7
F00H FFFH
L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 5 b its N o te : n ra n g e s fro m 0 to F
Program Memory Table Location *11 P11 1 *10 P10 1 *9 P9 1 *8 P8 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Instruction TABRDC [m] TABRDL [m]
Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits For the HT48R01, the table address location is 10 bits, i.e. from *9~*0 For the HT48R02, the table address location is 11 bits, i.e. from *10~*0 For the HT48R03, the table address location is 12 bits, i.e. from *11~*0 Rev. 1.00 7 December 20, 2006 P11~P8: Current program counter bits
HT48R01/HT48R02/HT48R03
word are transferred to the lower portion of TBLH, and the remaining 2 bits are read as 0. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR, and errors may occur. Therefore, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt is supposed to be disabled prior to the table read instruction. It will not be enabled until the TBLH has been backed up. All table related instructions require two cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register - STACK This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organised up to 8 levels and is neither part of the data nor part of the program space, and is neither readable nor writable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return RET or RETI instruction, the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, a stack overflow occurs and the first entry will be los. Only the most recent 4 return addresses are stored. Data Memory - RAM The data memory is divided into two functional groups: special function registers and general purpose data memory 648 for the HT48R01, 968 for the HT48R02 or 1608 for the HT48R03. Most are read/write, but some are read only. The unused space before 20H is reserved for future expanded usage and reading these locations will get 00H. The general purpose data memory, addressed from 20H to 5FH (HT48R01), 20H to 7FH (HT48R02) or 20H to BFH (HT48R03), is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through memory pointer register (MP;01H). Indirect Addressing Register Location 00H/02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H]/[02H] accesses data memory pointed to by MP0 (01H)/MP1 (03H). Reading location 00H itself indirectly will return the result 00H. Writing indirectly results in no operation. The memory pointer registers (MP0/MP1) are 7-bit registers (HT48R01/HT48R02) or 8 bit registers (HT48R03). The bit 7 of MP0/MP1 (HT48R01/ HT48R02) are undefined and reading will return the result 1. Any writing operation to MP0/MP1 will only transfer the lower 7-bit data to MP. Accumulator The accumulator is closely related to ALU operations. It is also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of data operations but also changes the status register.
Rev. 1.00
8
December 20, 2006
HT48R01/HT48R02/HT48R03
H T48R 01 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H PA PAC PAPU PAW K CTRL W CON ACC PCL TBLP TBLH W DTS STATUS IN T C 0 TM R0 TM R0C S p e c ia l P u r p o s e D a ta M e m o ry In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H :U nused, re a d a s "0 0 " 7FH TM R1 TM R1C PA PAC PAPU PAW K CTRL W CON ACC PCL TBLP TBLH W DTS STATUS IN T C 0 TM R0 TM R0C S p e c ia l P u r p o s e D a ta M e m o ry H T48R 02 In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H :U nused, re a d a s "0 0 " BFH TM R1 TM R1C PA PAC PAPU PAW K CTRL W CON ACC PCL TBLP TBLH W DTS STATUS IN T C 0 TM R0 TM R0C S p e c ia l P u r p o s e D a ta M e m o ry H T48R 03 In d ir e c t A d d r e s s in g R e g is te r 0 MP0 In d ir e c t A d d r e s s in g R e g is te r 1 MP1
5FH
G e n e ra l P u rp o s e D a ta M e m o ry (6 4 B y te s )
G e n e ra l P u rp o s e D a ta M e m o ry (9 6 B y te s )
G e n e ra l P u rp o s e D a ta M e m o ry (1 6 0 B y te s )
:U nused, re a d a s "0 0 "
RAM Mapping Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register Bit No. 0 Label C will not change the TO or PDF flag. In addition operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the CLR WDT or HALT instruction. The PDF flag can be affected only by executing the HALT or CLR WDT instruction or a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. Function C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PDF is cleared by system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status (0AH) Register Rev. 1.00 9 December 20, 2006
1 2 3 4 5 6~7
AC Z OV PDF TO 3/4
HT48R01/HT48R02/HT48R03
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly.
System Control Register Bit No. Label Function
0
Clock mode selection - select the system clock source 0: High speed clock as system clock - internal RC CLKMOD 1: Low speed clock as system clock - 32.768kHz, and RC oscillator stop Note: This selection is used only in internal RC + RTC mode. QOSC 32768Hz OSC quick start-up oscillating setting 0: quickly startup 1: slow startup BZ/BZ enable/disable 00: both disabled 01: Reserved 10: BZ only enabled 11: BZ and BZ enabled When BZ or BZ are disabled, the I/O port will have general I/O functions. If enabled, the BZ or BZ outputs will still be controlled by the related I/O port control and data settings. Refer to the I/O chapter for details. Unused bit, read as 0 BZCS, buzzer clock source, 0/1: Timer0/Timer1 Unused bit, read as 0 CTRL (16H) Register
1
2 3
BZEN0 BZEN1
4~5 6 7
3/4 BZCS
Note: For the HT48R01, BZCS is always 0 no matter what value is written into it; i.e., clock source for Buzzer is only from timer0.
Interrupt The device provides an external interrupt and internal timer/event counter interrupts. The Interrupt Control Register (INTC;0BH) contains the interrupt control bits to set the enable or disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, by clearing the EMI bit. This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit in the INTC register may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full.
All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. External interrupts are triggered by a high to low transition of INT and the related interrupt request flag (EIF; bit 4 of INTC) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts.
Rev. 1.00
10
December 20, 2006
HT48R01/HT48R02/HT48R03
The internal timer/event counter interrupt is initialised by setting the timer/event counter interrupt request flag (TF; bit 5 of INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag,TF, will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External Interrupt Timer/Event Counter 0 Overflow Priority 1 2 Vector 04H 08H Interrupt Source External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Priority 1 2 3 Vector 04H 08H 0CH
Interrupt Subroutine Vector for HT48R02/HT48R03 Once the interrupt request flags (T0F/ T1F, EIF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that a program does not use the CALL subroutine within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the CALL operates in the interrupt subroutine. Oscillator Configuration There are 4 different oscillator modes implemented in the microcontroller, which are selected by configuration options. All of them are designed for system clocks, namely the external RC oscillator (ERC), external crystal oscillator (ECRY), internal RC oscillator with I/O(IRC) and internal RC oscillator with RTC OSC (IRC+RTC). No matter what oscillator type is selected, the signal provides the system clock. The Power-down mode stops the system oscillator, except for the RTC oscillator, and resists external signals to conserve power. Function
Interrupt Subroutine Vector for HT48R01
Bit No. 0 1 2 3, 6~7 4 5
Label EMI EEI ET0I 3/4 EIF T0F
Controls the master (global) interrupt (1= enabled; 0= disabled) Controls the external interrupt (1= enabled; 0= disabled) Controls the timer/event counter 0 interrupt (1= enabled; 0= disabled) Unused bit, read as 0 External interrupt request flag (1= active; 0= inactive) Internal timer/event counter 0 request flag (1= active; 0= inactive) INTC 0 (0BH) Register for HT48R01
Bit No. 0 1 2 3 4 5 5 7
Label EMI EEI ET0I ET1I EIF T0F T1F 3/4
Function Controls the master (global) interrupt (1= enabled; 0= disabled) Controls the external interrupt (1= enabled; 0= disabled) Controls the timer/event counter 0 interrupt (1= enabled; 0= disabled) Controls the timer/event counter 1 interrupt (1= enabled; 0= disabled) External interrupt request flag (1= active; 0= inactive) Internal timer/event counter 0 request flag (1= active; 0= inactive) Internal timer/event counter 1 request flag (1= active; 0= inactive) Unused bit, read as 0 INTC 0 (0BH) Register for HT48R02/HT48R03
Rev. 1.00
11
December 20, 2006
HT48R01/HT48R02/HT48R03
If the configuration options select the IRC+RTC, the device supports two kinds of system clock. When combined with the Power-down function, it forms three operation modes. The two kinds of system clock are internal RC oscillator or RTC OSC (32768Hz) which is selected by the CTRL register CLKMOD bit. The three operation modes are named as Normal, Slow, or Idle mode. The following tables shows their relationship. If an RC oscillator is used, an external resistor between OSC1 and VDD is required whose resistance must range from 24kW to 1.5MW. The RC oscillator provides the most cost effective solution. The frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. If the crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are demanded. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to obtain a frequency reference, but two external capacitors connected to OSC1 and OSC2 are required. If an internal RC oscillator is used, OSC1 and OSC2 can be selected as general I/O lines or as a 32768Hz crystal (RTC) oscillator. The frequencies of internal oscillator can be 12MHz, 8MHz and 4MHz which is selected by configuration options. The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by configuration options to conserve power. Watchdog Timer - WDT The WDT clock source may come from a dedicated RC oscillator (WDT oscillator), RTC clock or instruction clock (system clock divided by 4) which is determined by option. This timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by options. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. The RTC clock is enabled only in the internal RC+RTC mode. The WDT clock (fS) is further divided by an internal counter to give longer watchdog time-outs. Once the internal WDT oscillator (RC oscillator with a period of 65ms at 5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of approximately 17ms at 5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1 and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.1s at 5V seconds. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. Bit No. 0~2 3~7 Label WS0~ WS2 3/4 Function WDT prescaler rate select Unused bit, read as 0
WDTS (09H) Register HALT Instruction During run state (HALT not execute) During run state (HALT execute) CLKMOD 0 1 x
V
DD
RC Oscillator On Off Off
32768Hz On On On
System Clock RC oscillator 32768Hz HALT
Mode Normal Slow Idle
OSC1
OSC1
PA6
OSC2 C r y s ta l O s c illa to r ( In c lu d e 3 2 7 6 8 H z ) RC
PA5 O s c illa to r
PA5 In te rn a l R C O s c illa to r
System Oscillator Rev. 1.00 12 December 20, 2006
HT48R01/HT48R02/HT48R03
fS
YS
/4 ROM Code O p tio n
fS
W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
fR T C W DTOSC
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
WS2 0 0 0 0 1 1 1 1
WS1 0 0 1 1 0 0 1 1
WS0 0 1 0 1 0 1 0 1
Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
Bit No.
Label
Function
6~7
External interrupt edge selection (default=10) INTES0~ 00: disable INTES1 01: rising edge trigger 10: falling edge trigger 11: dual edge trigger WCON (17H) Register
Power Down Operation - HALT The HALT mode is initialised by the HALT instruction and results in the following...
* The system oscillator will be turned off but the WDT
The WDT overflow under normal operation will initialise a chip reset and set the status bit TO. But in the HALT mode, the overflow will initialise a warm reset, and only the Program Counter and SP are reset to zero. To clear the contents of WDT (including the WDT prescaler), three methods are adopted; external reset (a low level to RES), software instruction and a HALT instruction. The software instruction include CLR WDT and the other set - CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the option - CLR WDT times selection option. If the CLR WDT is selected (i.e. CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. The WDT control register contains 4 bits of WDT enable bits. WDT can be enable by either WDT mask option or WDT control register (WDTEN[3:0]=0101B) and be disable by both being disable. Bit No. Label Function
oscillator keeps running (if the WDT oscillator is selected).
* The contents of the on chip RAM and registers remain
unchanged.
* WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator). * All of the I/O ports maintain their original status.
* The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialisation and the WDT overflow performs a warm reset. After the TO and PDF flags are examined, the reason for chip reset can be determined. The PDF flag is cleared by system power-up or executing the CLR WDT instruction and is set when executing the HALT instruction. The TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer; the others keep their original status. Both port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakened by an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to
0~3
Bit3~0, WDTEN3~WDTEN0= 1010B: WDT disable WDTEN0~ others: enable (using 0101B to WDTEN3 enable WDT is strongly recommended for the highest noise immunity) 3/4 Unused bit, read as 0
4~5
Rev. 1.00
13
December 20, 2006
HT48R01/HT48R02/HT48R03
1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period will be inserted after wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. To minimise power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
100kW RES 10kW 0 .1 m F *
The functional unit chip reset status are shown below. Program Counter Interrupt Prescaler WDT Timer/Event Counter Input/Output Ports Stack Pointer 000H Disable Clear Clear. After master reset, WDT begins counting Off Input mode Points to the top of the stack
V
DD
0 .0 1 m F *
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the Program Counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO 0 u 0 1 1 PDF 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
Reset Circuit Note: * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference.
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Note: u means unchanged To guarantee that the system oscillator is started and stabilised, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will enable the SST delay. An extra option load time delay is added during a system reset (power-up, WDT time-out during normal mode or RES reset).
Reset Timing Chart
HALT W DT
RES
W a rm
R eset
OSC1
SST 1 0 - b it R ip p le C o u n te r S y s te m R eset
C o ld R eset
Reset Configuration
Rev. 1.00
14
December 20, 2006
HT48R01/HT48R02/HT48R03
The register states are summarised in the following table. Register Program Counter MP0 (HT48R01/02) MP1 (HT48R01/02) MP0 (HT48R03) MP1 (HT48R03) ACC TBLP TBLH WDTS STATUS INTC0 (HT48R01) INTC0 (HT48R02/03) TMR0 TMR0C TMR1 TMR1C PA PAC PAPU PAWK CTRL WCON Reset (Power-on) 000H 1xxx xxxx 1xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --xx xxxx ---- -111 --00 xxxx --00 -000 -000 0000 xxxx xxxx 0000 1000 xxxx xxxx 0000 1--1111 1111 1111 1111 -000 0000 -000 0000 -0-- 0000 10-- 1010 WDT time-out RES Reset (Normal Operation) (Normal Operation) 000H 1uuu uuuu 1uuu uuuu xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu --uu uuuu ---- -111 --1u uuuu --00 -000 -000 0000 xxxx xxxx 0000 1000 xxxx xxxx 0000 1--1111 1111 1111 1111 -000 0000 -000 0000 -0-- 0000 10-- 1010 000H -uuu uuuu -uuu uuuu xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu --uu uuuu ---- -111 --uu uuuu --00 -000 -000 0000 xxxx xxxx 0000 1000 xxxx xxxx 0000 1--1111 1111 1111 1111 -000 0000 -000 0000 -0-- 0000 10-- 1010 RES Reset (HALT) 000H -uuu uuuu -uuu uuuu xxxx xxxx xxxx xxxx uuuu uuuu uuuu uuuu --uu uuuu ---- -111 --01 uuuu --00 -000 -000 0000 xxxx xxxx 0000 1000 xxxx xxxx 0000 1--1111 1111 1111 1111 -000 0000 -000 0000 -0-- 0000 10-- 1010 WDT Time-out (HALT)* 000H 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu ---- -uuu --11 uuuu --uu -uuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uuuu uuuu -uuu uuuu -uuu uuuu -u-- uuuu uu-- uuuu
Note: * means warm reset - not implement u means unchanged x means unknown
Rev. 1.00
15
December 20, 2006
HT48R01/HT48R02/HT48R03
Timer/Event Counter One or two timer/event counters are implemented in the microcontroller. The timer/event counter contains an 8-bit programmable count-up counter and the clock may come from an external source, the system clock or RTC clock. Using an external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base, while using the internal clock allows the user to generate an accurate time base. The timer/event counter can generate a buzzer signal by using an external or internal clock. There are 2 registers related to the timer/event counter; TMR0 [0DH], TMR0C [0EH] (TMR1 [10H]), TMR1C [11H]). Two physical registers are mapped to the TMR location; writing TMR0 (TMR1) places the start value into the timer/event counter preload register while reading TMR0 (TMR1) retrieves the contents of the timer/event counter. The TMR0C (TMR1C) is a timer/ event counter control register, which defines some options. The T0M0, T0M1 (T1M0, T1M1) bits define the operating mode. The event count mode is used to count external events, which means the clock source comes from an external TMR0 (TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the fINT clock. The pulse width measurement mode can be used to count the high or low level duration of the external signal TMR0 (TMR1). The counting is based on the fINT clock. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register and generates an interrupt request flag (T0F; bit 5 of INTC0 or T1F bit 6 of INTC0) at the same time. In the pulse width measurement mode with the values of T0ON and T0E ( T1ON and T1E) equal to 1, after the TMR0 (TMR1) has received a low to high transient (or high to low if T0E (T1E) is 0), it will start counting until TMR0 (TMR1) returns to its original level and resets T0ON (T1ON). The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only a single cycle measurement can be implemented. Not until the T0ON (T1ON) bit has been set again, will the cycle measurement function again as long as it receives further transient pulses. Note that, in this operating mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. In the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. To enable the counting operation, the timer ON bit, T0ON (T1ON) should be set to 1. In the pulse width measurement mode, the T0ON (T1ON) will be cleared automatically after the measurement cycle is completed. But in the other two modes the T0ON (T1ON) can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disable the interrupt service.
fS
YS
M U
fT
P
RTC OSC
X
7 - s ta g e P r e s c a le r 8 -1 M U X f IN
T
D a ta B u s T0M 1 T0M 0 T0E 8 - b it T im e r /E v e n t C o u n te r R e lo a d P r e lo a d R e g is te r
T0S T0PSC 2~T0PSC 0 TM R0
T0M 1 T0M 0 T0O N
P u ls e W id th M e a s u re m e n t M o d e C o n tro l
8 - b it T im e r /E v e n t C o u n te r 0 (T M R 0 ) 1 /2
O v e r flo w to In te rru p t BZ0
Timer/Event Counter 0
fS RTC /4 M U X TM R1 T1E T1M 1 T1M 0 T1O N P u ls e W id th M e a s u re m e n t M o d e C o n tro l 8 - b it T im e r /E v e n t C o u n te r 1 (T M R 1 ) 1 /2 O v e r flo w to In te rru p t BZ1
YS
D a ta B u s T1M 1 T1M 0 8 - b it T im e r /E v e n t C o u n te r R e lo a d P r e lo a d R e g is te r
OSC
T1S
Timer/Event Counter 1 - HT48R02/HT48R03 only Rev. 1.00 16 December 20, 2006
HT48R01/HT48R02/HT48R03
In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. The timer/event counter will still operate until overflow occurs. When the timer/event counter is read, the clock will be blocked to avoid errors. As clock blocking may reBit No. Label sults in a counting error, this must be taken into consideration by the programmer. The bit 0~2 of the TMR0C can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. The definitions are as shown. The timer/event counter overflow signals can be used to generate signals for the buzzer. Function To define the prescaler stages, T0PSC2, T0PSC1, T0PSC0= 000: fINT=fTP 001: fINT=fTP/2 010: fINT=fTP/4 011: fINT=fTP/8 100: fINT=fTP/16 101: fINT=fTP/32 110: fINT=fTP/64 111: fINT=fTP/128 To define the TMR active edge of the timer/event counter In event counter mode (T0M1,T0M0)=(0,1): 1: count on falling edge 0: count on rising edge In pulse width measurement mode (T0M1,T0M0)=(1,1): 1: start counting on rising edge, stop on falling edge 0: start counting on falling edge, stop on rising edge To enable or disable timer counting (0=disabled; 1=enabled) Timer clock source selection 0: fSYS 1: RTC To define the operating mode (T0M1, T0M0) 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH) Register Bit No. 0~2 Label 3/4 Unused bit, read as 0 To define the TMR active edge of the timer/event counter In event counter mode (T1M1,T1M0)=(0,1): 1: count on falling edge 0: count on rising edge In pulse width measurement mode (T1M1,T1M0)=(1,1): 1: start counting on rising edge, stop on falling edge 0: start counting on falling edge, stop on rising edge To enable or disable timer counting (0=disabled; 1=enabled) Timer clock source selection 0: fSYS/4 1: RTC To define the operating mode (T1M1, T1M0) 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register Rev. 1.00 17 December 20, 2006 Function
0~2
T0PSC0~ T0PSC2
3
T0E
4 5
T0ON T0S
6 7
T0M0 T0M1
3
T1E
4 5
T1ON T1S
6 7
T1M0 T1M1
HT48R01/HT48R02/HT48R03
Input/Output Ports There are 7 bi-directional input/output lines and 1 input line in the microcontroller, labeled as PA, which are mapped to the data memory of [12H]. All of the I/O ports can be used for input or output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC) to control the input/output configuration (PA7 for input only). With this control register, a CMOS output or Schmitt trigger input ( with or without pull-high resistor structures) can be reconfigured dynamically (i.e. on-the-fly) under software control ( the PA7 only provide input mode). To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS is the only configuration. These control register is mapped to locations 13H. After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator.
* Wake up and pull-high function
Each line (except PA7) of PA port supports waking-up MCU and pull-high function which are controlled by PAWK, PAPU registers respectively. PA7 hasnt wake-up and pull-high function. Bit No. Label Function
0~6
PAWKn= 0, PAn wake-up is disPAWK0~ able PAWK6 PAWKn=1, PAn wake-up is enable 3/4 Unused bit, read as 0
7
PAWK (15H) Register Bit No. 0~6 7 Label Function
PAPU0~ PAPUn= 0, PAn pull-up is disable PAPU6 PAPUn=1, PAn pull-up is enable 3/4 Unused bit, read as 0 PAPU (14H) Register
V
DD
PAPU 6~PAPU 0 D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D a ta B it Q D CK S Q M (P A 1 , P A 0 ) (B Z , B Z ) M U X PAW K6~PAW K0 R e a d D a ta R e g is te r S y s te m W a k e - u p ( P A 0 ~ P A 6 o n ly ) IN T fo r P A 3 o n ly T M R fo r P A 2 o n ly BZEN U X C o n tr o l B it Q D CK S Q PA0 PA1 PA2 PA3 PA4 PA5 PA6 /B Z /B Z /T M /IN T /T M /O S /O S
R0 R1 C2 C1
W r ite D a ta R e g is te r
(P A 0 /P A 1 )
Input/Output Ports (PA0~PA6)
R e a d D a ta D a ta B u s R E S fo r P A 7 o n ly PA7
Input/Output Ports (PA7)
Rev. 1.00
18
December 20, 2006
HT48R01/HT48R02/HT48R03
* Buzzer Function
Low Voltage Reset - LVR The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~VLVR, such as when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications:
* The low voltage (0.9V~VLVR) has to remain in this con-
PA0 and PA1 are pin-shared with the BZ and BZ buzzer signals, respectively. If the Buzzer option is selected, then if these pins are setup as outputs, the signals on PA0 (or PA1) will be the Buzzer signal. If setup as inputs, they will always retain their original input functions. The buzzer output signals (in output mode) are controlled by the PA0 data register only. The truth table for PA0/BZ and PA1/BZ are listed below. Port A also has a CMOS or Schmitt trigger input configuration option (All port A I/O lines are controlled by a option bit). The truth table for PA0/BZ and PA1/BZ is as shown. PA0 I/O PA1 I/O PA0 Mode PA1 Mode PA0 Data PA1 Data I I I I OOOOOOOO I I OOOOO
dition for a time greater than 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
* The LVR uses an OR function with the external RES
signal to perform a chip reset. I OOO I The relationship between VDD and VLVR is shown below.
VDD 5 .5 V V
OPR
x x x xCBBCBBBB xCBBx xxCCCBB x x 0 1 D 0 1 D0 0 1 0 1 x D x x x x x D1 D D x x
5 .5 V
VDD 5 .5 V
V
OPR
5 .5 V
VDD 5 .5 V
V
OPR
5 .5 V
V 2 .1 V 2 .2 V
LVR
V 3 .1 5 V 2 .2 V
LVR
V 4 .2 V 2 .2 V
LVR
PA0 Pad Status I
I
I
I D 0 B D0 0 B 0 B I I D1 D D 0 B
PA1 Pad Status I D 0 B I
Note: I: input; O: output; D, D0, D1: data; B: buzzer option, BZ or BZ; x: don't care C: CMOS output
0 .9 V
0 .9 V
0 .9 V
Note: VOPR is the voltage range for proper chip operation with a 4MHz system clock.
V 5 .5 V
DD
V
LVR
L V R D e te c t V o lta g e
0 .9 V 0V R e s e t S ig n a l
R eset *1
N o r m a l O p e r a tio n *2
R eset
Low Voltage Reset Note: *1: To make sure that the system oscillator has stabilised, the SST provides an extra delay of 1024 system clock pulses before entering normal operation. *2: Since the low voltage has to be maintained in its original state and exceed tLVR, therefore a tLVR delay enters the reset mode.
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Configuration Options The following table shows the various configuration options for the microcontroller. All options must be defined for proper system functioning. Items System oscillator selection
* Internal RC + PA5/PA6
Options
1
* Internal RC + RTC * External Xtal * External RC + PA5
2 3 4 5 6 7 8
Internal RC frequency selection: 4MHz, 8MHz or 12MHz WDT function: enable or disable WDT clock source: WDTOSC, fSYS/4 or RTC OSC CLRWDT instruction(s): one or two clear WDT instruction(s) LVR function: enable or disable LVR selection: 2.1V/3.15V/4.2V RES or PA7 input selection
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HT48R01/HT48R02/HT48R03
Application Circuits
V
DD
R
OSC
470pF C1
OSC1 PA5 OSC1
R C S y s te m O s c illa to r 2 4 k W < R O S C < 1 .5 M W
V
C2
DD
0 .0 1 m F * 100kW 0 .1 m F
R1 VDD R E S /P A 7 P A 0 /B Z P A 1 /B Z P A 2 /T M R 0 VSS P A 3 /IN T P A 4 /T M R 1
OSC2
C r y s ta l S y s te m O s c illa to r F o r C 1 , C 2 a n d R 1 v a lu e s , s e e ta b le b e lo w
OSC1 10pF 32768H z OSC2
10kW
In te r n a l R C O s c illa to r + E x te rn a l R T C O S C
0 .1 m F *
OSC C ir c u it S e e R ig h t S id e
OSC1 OSC2
PA5 PA6
In te r n a l R C O s c illa to r T w o p in s a r e c o n fig u r e d a s I/O p in
H T 4 8 R 0 1 /H T 4 8 R 0 2 /H T 4 8 R 0 3
OSC
C ir c u it
Note: The resistance and capacitance for the reset circuit should be designed to ensure that VDD is stable and remains in a valid range of the operating voltage before bringing RES high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only) Crystal or Resonator 8MHz Crystal & Resonator 4MHz Crystal 4MHz Resonator 3.58MHz Crystal 3.58MHz Resonator 2MHz Crystal & Resonator 1MHz Crystal 480kHz Resonator 455kHz Resonator 429kHz Resonator 400kHz Resonator C1, C2 35pF 10pF 10pF 10pF 10pF 35pF 68pF 300pF 300pF 300pF 300pF R1 3.9kW 10kW 12kW 12kW 12kW 12kW 18kW 10kW 10kW 10kW 10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
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HT48R01/HT48R02/HT48R03
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
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HT48R01/HT48R02/HT48R03
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH (This instruction is not valid for HT48R05A-1/HT48C05) 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
Note: x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged.
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HT48R01/HT48R02/HT48R03
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TO 3/4 ADCM A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,[m] Description Operation Affected flag(s) TO 3/4 ADD A,x Description Operation Affected flag(s) TO 3/4 ADDM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
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HT48R01/HT48R02/HT48R03
AND A,[m] Description Operation Affected flag(s) TO 3/4 AND A,x Description Operation Affected flag(s) TO 3/4 ANDM A,[m] Description Operation Affected flag(s) TO 3/4 CALL addr Description PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack Program Counter+1 Program Counter addr
Operation Affected flag(s)
TO 3/4 CLR [m] Description Operation Affected flag(s) TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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HT48R01/HT48R02/HT48R03
CLR [m].i Description Operation Affected flag(s) TO 3/4 CLR WDT Description Operation Affected flag(s) TO 0 CLR WDT1 Description PDF 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared. WDT 00H PDF and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CLR WDT2 Description
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged. WDT 00H* PDF and TO 0*
Operation Affected flag(s)
TO 0* CPL [m] Description Operation Affected flag(s) TO 3/4
PDF 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
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HT48R01/HT48R02/HT48R03
CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TO 3/4 DAA [m] Description
PDF 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TO 3/4 DEC [m] Description Operation Affected flag(s) TO 3/4 DECA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
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HT48R01/HT48R02/HT48R03
HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared. Program Counter Program Counter+1 PDF 1 TO 0
Operation
Affected flag(s) TO 0 INC [m] Description Operation Affected flag(s) TO 3/4 INCA [m] Description Operation Affected flag(s) TO 3/4 JMP addr Description Operation Affected flag(s) TO 3/4 MOV A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Program Counter addr PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
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HT48R01/HT48R02/HT48R03
MOV A,x Description Operation Affected flag(s) TO 3/4 MOV [m],A Description Operation Affected flag(s) TO 3/4 NOP Description Operation Affected flag(s) TO 3/4 OR A,[m] Description Operation Affected flag(s) TO 3/4 OR A,x Description Operation Affected flag(s) TO 3/4 ORM A,[m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. Program Counter Program Counter+1 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
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HT48R01/HT48R02/HT48R03
RET Description Operation Affected flag(s) TO 3/4 RET A,x Description Operation Affected flag(s) TO 3/4 RETI Description Operation Affected flag(s) TO 3/4 RL [m] Description Operation Affected flag(s) TO 3/4 RLA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. Program Counter Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. Program Counter Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
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HT48R01/HT48R02/HT48R03
RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TO 3/4 RLCA [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TO 3/4 RR [m] Description Operation Affected flag(s) TO 3/4 RRA [m] Description Operation Affected flag(s) TO 3/4 RRC [m] Description Operation PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
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HT48R01/HT48R02/HT48R03
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TO 3/4 SBC A,[m] Description Operation Affected flag(s) TO 3/4 SBCM A,[m] Description Operation Affected flag(s) TO 3/4 SDZ [m] Description PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TO 3/4 SDZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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HT48R01/HT48R02/HT48R03
SET [m] Description Operation Affected flag(s) TO 3/4 SET [m]. i Description Operation Affected flag(s) TO 3/4 SIZ [m] Description PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TO 3/4 SIZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TO 3/4 SNZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
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HT48R01/HT48R02/HT48R03
SUB A,[m] Description Operation Affected flag(s) TO 3/4 SUBM A,[m] Description Operation Affected flag(s) TO 3/4 SUB A,x Description Operation Affected flag(s) TO 3/4 SWAP [m] Description Operation Affected flag(s) TO 3/4 SWAPA [m] Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O PDF 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
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HT48R01/HT48R02/HT48R03
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZA [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TO 3/4 SZ [m].i Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TO 3/4 TABRDC [m] Description Operation Affected flag(s) TO 3/4 TABRDL [m] Description
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Note that this instruction is not valid for HT48R05A-1/HT48C05 [m] ROM code (low byte) TBLH ROM code (high byte)
Operation Affected flag(s)
TO 3/4
PDF 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.00
35
December 20, 2006
HT48R01/HT48R02/HT48R03
XOR A,[m] Description Operation Affected flag(s) TO 3/4 XORM A,[m] Description Operation Affected flag(s) TO 3/4 XOR A,x Description Operation Affected flag(s) TO 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 PDF 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 1.00
36
December 20, 2006
HT48R01/HT48R02/HT48R03
Package Information
10-pin MSOP Outline Dimensions
10
6 E1
1
5
D A e R 0 .1 0 B (4 C O R N E R S ) A1 L A2 C
E
q
L1
Symbol A A1 A2 B C D E E1 e L L1 q
Dimensions in mm Min. 3/4 0 0.75 0.17 3/4 3/4 3/4 3/4 3/4 0.4 3/4 0 Nom. 3/4 3/4 3/4 3/4 3/4 3 4.9 3 0.5 3/4 0.95 3/4 Max. 1.1 0.15 0.95 0.27 0.25 3/4 3/4 3/4 3/4 0.8 3/4 8
Rev. 1.00
37
December 20, 2006
HT48R01/HT48R02/HT48R03
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holmate.com
Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
38
December 20, 2006

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